1. Field of the Invention
The present invention relates to a chopper circuit, a chopper circuit control method, a chopper-type charging circuit, an electronic device, and a timekeeping apparatus.
2. Related Art
A chopper-type charging circuit is known as a charging circuit for charging a capacitor or a battery, with alternating current electrical power generated by an electrical generator.
FIG. 12 of the appended drawings is a circuit diagram of a chopper-type charging circuit. This chopper-type charging circuit 1 is formed by an oscillator circuit 2, which outputs a clock signal CL, and comparators COM1 and COM2, which perform a comparison between the voltages at output terminals A and B of an alternating current electrical generator AG and a terminal voltage VDD of a power supply, and an AND circuit 3, which calculates the logical product of the output signals SP1 and SP2 of the comparators COM1 and COM2 and the clock signal CL.
The chopper-type charging circuit also has a large-capacitance capacitor 4 for storing a charging current, and P-channel FETs P1 and P2, which are on/off controlled by the output signals SP1 and SP2 of the comparators COM1 and COM2, and N-channel FETs N1 and N2, which are on/off controlled by an output signal SN of the AND circuit 3.
In this configuration, diodes D1, D2, D3, and D4 are parasitic diodes of the P-channel FETs P1 and P2 and the N-channel FETs N1 and N2, respectively.
The operation of the chopper-type charging circuit is described below, with reference made to the timing diagram shown in FIG. 13.
In FIG. 13, the assumption is that until a time ta, the voltages at the output terminals A and B is no greater than the terminal voltage VDD, the comparator COM1 and COM2 output signals SP1 and SP2 being held at a high level, and the P-channel FETs P1 and P2 being in the off state.
At the time ta, when the clock signal CL changes to the high level, the output signal SN of the AND circuit 3 changes to the high level, so that the N-channel FETs N1 and N2 change to the on state, a closed loop being formed by the alternating current generator AG and the N-channel FETs N1 and N2.
In the above case, the alternating current generator AG generates an electromotive force and, for example, when the output terminal A reaches a positive potential with respect to the output terminal B, as shown by the symbol .alpha. in FIG. 12, a current i1 flows through a path from the alternating current generator AG, to the N-channel PET N1, and then to the N-channel FET N2.
At the time tb, when the clock signal CL falls to the low level, the output signal SN of the AND circuit 3 changes to the low level, so that the N-channel FETs N1 and N2 are placed in the off state, thereby cutting off the above-noted current path.
In the above case, because of the current that flows during the time when the clock signal CL is at the high level (hereinafter referred to as the shorted period), the energy is stored in the inductance of the generator coil of the alternating current generator AG, this energy causing a rise in the voltage at the output terminal A.
Next, at the time tc, when the voltage on the terminal A rises to above the terminal voltage VDD of the large-capacitance capacitor 4, the output signal SP1 of the comparator COM1 changes to the low level, so that the P-channel FET P1 switches to the on state.
As a result, as shown by the symbol .beta. in FIG. 12, a current i2 flows through a current path from the diode D4 of the N-channel FET N2, to the alternating current generator AG, to the P-channel FET P1, and then to the large-capacitance capacitor 4. Thus, the charging of the large-capacitance capacitor 4 begins.
As the charging continues, energy stored in the inductance of the generator coil is gradually released, so that the charging current i2 gradually decreases. When the voltage on the output terminal A falls below the terminal voltage VDD of the large-capacitance capacitor 4, the output signal SP1 of the comparator COM1 changes to the high level, so that the P-channel FET P1 switches to the off state, thereby cutting off the above-noted charging current path.
That is, until the voltage at the output terminal A falls below the terminal voltage VDD of the large-capacitance capacitor 4, the AND circuit 3 holds the N-channel FETs N1 and N2 in the off state, so that charging is continued. Additionally, when the amount of electricity generated by the alternating current generator AG is large and the amount of energy stored in the inductance of the generator coil is large, charging continues even after switching to the shorted period, thereby making the charging time long, so that it commensurately eats away the shorted period.
In the case in which the electromotive force of the alternating current generator AG is generated and the output terminal B reaches a potential that is positive potential with respect to the output terminal A, the direction of the current i1 flowing during the above-noted shorted period reverses, so that the voltage on the output terminal B rises. As a result, the charging current i2 flows through the path from the diode D3 of the N-channel FET N1, and the alternating current generator AG, and the P-channel FET P2, and then the large-capacitance capacitor 4, resulting in the charging of the large-capacitance capacitor 4.
Thus, in a chopper-type charging circuit of the past, by repeatedly performing shorting and voltage rise of the circuit in accordance with the clock signal, the electromotive force of an alternating current generator, which has a small, non-uniform amount of generated electricity, is converted to a chopper voltage that charges a large-capacitance capacitor. In the case in which there is a large amount of energy stored in the inductance of the generator coil of the chopper-type charging circuit 1, or in which the input energy is large, the shorted period of the chopper is disabled, so that priority is given to charging by non-chopped operation. By performing charging by switching between chopper and non-chopped operation, it is possible to efficiently charge the large-capacitance capacitor.
In a chopper-type charging circuit using a unidirectional unit having a configuration in the voltage across the terminals of this type of field-effect transistor is comparator using a comparator, one method of that can be envisioned of improving the charging efficiency by reducing charging path loss is that of making the conduction resistance (on-state resistance) between the source and drain of the field-effect transistor as small a value as possible.
However, if this conduction resistance is made small, the source-drain voltage of the field-effect transistor is becomes small. Therefore, the potential at the collector input terminal falls below a threshold value, and the field-effect transistor goes into the off state, after which the difference in potential between the two input terminals of the comparator rises because of the forward voltage drop of the diode, resulting in the field-effect transistor immediately going into the on state, with this operation being repeated. In the case of such low-current conduction, a phenomenon known as chattering occurs, in which the field-effect transistor repeated alternates between the on and off states.
That is, at the time td in the timing diagram of FIG. 13, when the voltage on the output terminal A falls below the terminal voltage VDD of the large-capacitance capacitor 4, the output signal SP1 of the comparator COM1 changes to the high level, and the P-channel FET P1 goes into the off state. However, because the charging current i2 flowing in the P-channel FET P1 immediately before the switching of the output signal SP1 of the comparator COM1 to the high level (the region of time td) is small, the voltage drop due to the on resistance oft eh P-channel FET P1 is small. For this reason, when the signal SP1 changes to the high level and the P-channel FET P1 switches to the off state, because of the forward voltage drop of the diode D1, there is a rise in the potential difference between the two input terminals of the comparator COM1. Then, at time te, the output signal SP1 of the comparator COM1 falls to the low level for a short amount of time (FIG. 13).
That is, the potential difference between the input terminals of the comparator COM1 differ, depending upon whether the P-channel FET P1 is off or on, so that the signal level of the signal SP1 switching frequently between the high level and the low level. Therefore, chattering occurs in which the P-channel FET P1 repeatedly switches between the on state and the off state.
If this type of chattering phenomenon occurs when the clock signal CL is in its high level period (shorted period), such as shown in FIG. 13, the signal level of the output signal SN of the AND circuit 3 is switched in response to the switching of the signal level of the signal SP1.
When this occurs, as shown in FIG. 13 the timing of the switching of the signal level of the output signal SN of the AND circuit 3 is slightly retarded with respect to the timing of the switching of the signal level of the signal SP1, because of the delay time of the AND circuit 3.
For this reason, in the case in which chattering occurs during the shorted period, there occurs a period of time during which the both the P-channel FET P1 and both of the N-channel FETs N1 and N2 are in the on state (period dt shown in FIG. 13).
In this case, because the voltage at the output terminals A and B is equal to or smaller than the positive-side voltage VDD on the large-capacitance capacitor 4, a through current flows from the large-capacitance capacitor 4, as shown by the symbol .gamma. in FIG. 13, so that the charging efficiency is reduced.
FIG. 14A is a waveform diagram of the current flowing in the chopper-type charging circuits 1, and FIG. 14B being an enlarged waveform diagram. It can be seen in these two waveform diagrams that the through current indicated above the ground reference center level is equal to or greater than the charging current indicated below the ground level reference.
For this reason, particularly in the case of a short charging time, the amount of discharge due to the through current is equal to or greater than the amount of charging obtained by the charging, resulting in a significant decrease in the charging efficiency.